1. Field of the Invention
The field of the present invention relates to a nonvolatile semiconductor memory device and a manufacturing method therefor, and more particularly to an electrically programmable metal-oxide-semiconductor (MOS) type nonvolatile semiconductor memory device having an asymmetrically placed source and drain.
2. Description of Related Art
Flash memories are a growing class of nonvolatile storage integrated circuits. Flash memories have the capability of electrically erasing, programming, and reading a memory cell in the chip. A flash memory cell is formed using so-called floating gate transistors in which the data is stored in a cell by charging or discharging the floating gate. The floating gate is a conductive material, typically polysilicon, which is insulated from the channel of the transistor by a thin layer of oxide, or other insulating material, and insulated from the control gate or word-line of the transistor by a second layer of insulating material.
Data is stored in the memory cell by charging or discharging the floating gate. The floating gate is charged through a Fowler-Nordheim (FN) tunneling mechanism by establishing a large positive voltage between the gate and source or drain. This causes electrons to be injected into the floating gate through the thin insulator. Alternatively, an avalanche injection mechanism may be used by applying potentials to induce high energy electrons in the channel of the cell which are injected across the insulator to the floating gate. When the floating gate is charged, the threshold voltage for causing the memory cell channel to conduct is increased above the voltage applied to the word-line during a read operation. Thus, when a charged cell is addressed during a read operation, the cell does not conduct. The non-conducting state of the cell can be interpreted as a binary 1 or 0 depending on the polarity of the sensing circuitry.
The floating gate is discharged to establish the opposite memory state. This function is typically carried out by FN tunneling between the floating gate and the source or the drain of the transistor, or between the floating gate and the substrate. For instance, the floating gate may be discharged through the source by establishing a large positive voltage from the source to the gate, while the drain is left at a floating potential.
A popular architecture for flash memories is the virtual ground bit-line structure. In a virtual ground architecture, the transistors of adjacent memory cell columns share a bit-line between the sources of the transistors of one of the columns and the drains of the transistors of the other of the adjacent columns. The need for a dedicated pair of bit-lines per column is eliminated. Any memory cell in the array can be programmed or read by application of appropriate voltages to the word-line and the bit-lines connected to it. In particular, the state of an addressed memory cell can be determined by sensing the current flowing through its source and drain by means of the bit-lines connected thereto. To further reduce the area required by the source and drain bit-lines, they can be implemented as buried diffusion bit-lines.
A drawback to buried bit-line virtual ground architectures in flash memory is the problem of an undesired disturb/program of an adjacent cell due to sharing a bit-line and a word-line with a cell being programmed or read. During programming of a cell, an adjacent cell may be susceptible to FN tunneling or hot electron injection. This results in an unacceptable memory loss. During a read of a cell, an adjacent cell may experience a leakage current, which will degrade the readout characteristic of the cell. The conventional approach to the disturb problem is to asymmetrically dope the source and drain of each transistor. This asymmetric doping does help the disturb problem, but has the drawback of increasing bit-line resistance. The increase in bit-line resistance in turn adversely affects the conductivity of the bit-lines, the power consumption and speed of the memory array.
The major challenge of flash memory design is to improve programming speed while maintaining disturb resistance. To realize further reductions in array size, new solutions to the disturb problem that do not involve increasing the bit-line resistance need to be found.